1. Field of the Invention
The present invention relates to a data readout circuit for semiconductor devices.
2. Description of the Related Art
JP-A 10-11974 (1998) discloses a circuit that amplifies data accumulated in a memory cell in a semiconductor device before reading the data out (see FIG. 7). In this circuit structure, drivers that have higher ability than the current driving ability of the pull-ups and the memory cells of data lines DL and DLB are provided for the respective data lines DL and DLB. With the drivers, the potentials of the data lines DL and DLB become equal to one another in the initial stage of a data readout operation (i.e., during the process of equalizing the data lines), and all the potentials are also stabilized at a predetermined level. The potentials of the data lines DL and DLB are set at a slightly lower level than normal, so that it becomes easier to saturate an N-type MOSFET, and the gain of the sense amplifier can be increased. In short, during the process of equalizing the data lines at the time of a data readout operation, the data line potentials are set at a predetermined level, and the operation speed of the sense amplifier can be increased.
However, there are the following problems with the above conventional data readout method.
A general memory device, such as a DRAM, a SRAM, or a flash memory, is designed to read out plural sets of data at the same time. To read out data from plural memory cells at the same time, a signal that serves as a reference with respect to the data to be read out from each of the memory cells is required. In the conventional structure shown in FIG. 7, the signal on the data lines DLB serves as a reference signal, with the signal on the data line DL representing the data read out from a memory cell. In this structure, it is necessary to prepare the same number of circuits for generating reference signals as the number of sets of data to be read out. This leads to an increase in chip area. To avoid the problem, a reference signal generating circuit may be shared among plural readout circuits. In the conventional circuit structure, however, the data lines DL from which data are to be read out at the same time are short-circuited to the reference line DLB in the initial stage of a data readout operation (i.e., during the process of equalizing the data lines). If a problem is caused in one of the data lines during the process in such a structure, the voltages at all the data lines DL become unstable, and the data cannot be properly read out from the other normal data lines, because all the other normal data lines DL from which data are to be read out at the same time are connected to the data line DL having the problem via the data line DLB serving as the reference data line.